`timescale 1ns / 1ps

module breath_led_tb ();

    reg clk_50m, rst_n;
    wire [3:0] led;

    initial begin
        $dumpfile("output/breath_led_tb.vcd");
        $dumpvars(0, breath_led_tb);
    end

    initial begin
        clk_50m = 0;
        rst_n = 0;
        #100 rst_n = 1;
        #1000_000_000 $stop;
    end

    always #10 clk_50m <= ~clk_50m;

    breath_led_top breath_led_top_inst (
        .sys_clk            (clk_50m),
        .sys_rst_n          (rst_n),
        .led                (led)
    );

endmodule  //delay_tb